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?2004 fairchild semiconductor corporation www.fairchildsemi.com rev.1.0.4 features ? internal avalanche rugged sense fet ? consumes only 0.65w at 240vac & 0.3w load with advanced burst-mode operation ? frequency modulation for low emi ? precision fixed operating frequency ? internal start-up circuit ? pulse by pulse current limiting ? abnormal over current protection ? over voltage protection ? over load protection ? internal thermal shutdown function ? auto-restart mode ? under voltage lockout ? low operating current (3ma) ? adjustable peak current limit ? built-in soft start applications ? smps for vcr, svr, stb, dvd & dvcd ? smps for printer, facsimile & scanner ? adaptor for camcorder description the fsdl0165rn is an integrated pulse width modulator (pwm) and sense fet specifically designed for high perfor- mance offline switch mode power supplies (smps) with minimal external components. this device is an integrated high voltage power switching regulator which combine an avalanche rugged sense fet with a current mode pwm control block. the integrated pwm controller features include: a fixed oscillator with frequency modulation for reduced emi, under voltage lock out (uvlo) protection, leading edge blanking (leb), optimized gate turn-on/turn- off driver, thermal shut down (tsd) protection, abnormal over current protection (aocp) and temperature compen- sated precision current sources for loop compensation and fault protection circuitry. when compared to a discrete mosfet and controller or rcc switching converter solu- tion, the fsdl0165rn reduce total component count, design size, weight and at the same time increases efficiency, productivity, and system reliability. this device is a basic platform well suited for cost effective designs of flyback converters. table 1. notes: 1. typical continuous power in a non-ven- tilated enclosed adapter measured at 50 c ambient. 2. maximum practical continuous power in an open frame design at 50 c ambient. 3. 230 vac or 100/115 vac with doubler. typical circuit figure 1. typical flyback application output power table product 230vac 15% (3) 85-265vac adapt- er (1) open frame (2) adapt- er (1) open frame (2) fsdl321 11w 17w 8w 12w FSDH321 11w 17w 8w 12w fsdl0165rn 13w 23w 11w 17w fsdm0265rn 16w 27w 13w 20w fsdh0265rn 16w 27w 13w 20w fsdl0365rn 19w 30w 16w 24w fsdm0365rn 19w 30w 16w 24w fsdl0165rl 13w 23w 11w 17w fsdm0265rl 16w 27w 13w 20w fsdh0265rl 16w 27w 13w 20w fsdl0365rl 19w 30w 16w 24w fsdm0365rl 19w 30w 16w 24w drain source vstr vfb vcc pwm ac in dc out ipk fsdl0165rn green mode fairchild power switch (fps tm )
fsdl0165rn 2 internal block diagram figure 2. functional block diagram of fsdl0165rn 8v/12v 2 6,7,8 1 3 vref internal bias s q q r osc vcc vcc i delay i fb v sd tsd vovp vcc vocp s q q r r 2.5r vcc good vcc drain v fb gnd aocp gate driver 5 vstr i start vcc good v burl /v burh leb pwm soft start + - 4 i pk freq. modulation v burh vcc i b_peak burst normal
fsdl0165rn 3 pin definitions pin configuration figure 3. pin configuration (top view) pin number pin name pin function description 1 gnd sense fet source terminal on primary side and internal control ground. 2vcc positive supply voltage input. although connected to an auxiliary transform- er winding, current is supplied from pin 5 (vstr) via an internal switch during startup (see internal block diagram section). it is not until vcc reaches the uvlo upper threshold (12v) that the internal start-up switch opens and de- vice power is supplied via the auxiliary transformer winding. 3vfb the feedback voltage pin is the non-inverting input to the pwm comparator. it has a 0.9ma current source connected internally while a capacitor and op- tocoupler are typically connected externally. a feedback voltage of 6v trig- gers over load protection (olp). there is a time delay while charging between 3v and 6v using an internal 5ua current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions. 4ipk pin to adjust the current limit of the sense fet. the feedback 0.9ma current source is diverted to the parallel combination of an internal 2.8k ? resistor and any external resistor to gnd on this pin to determine the current limit. if this pin is tied to vcc or left floating, the typical current limit will be 1.2a. 5vstr this pin connects directly to the rectified ac line voltage source. at start up the internal switch supplies internal bias and charges an external storage capacitor placed between the vcc pin and ground. once the vcc reaches 12v, the internal switch is disabled. 6, 7, 8 drain the drain pin is designed to connect directly to the primary lead of the trans- former and is capable of switching a maximum of 650v. minimizing the length of the trace connecting this pin to the transformer will decrease leak- age inductance. 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 45 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 gnd gnd gnd gnd vcc vcc vcc vcc vfb vfb vfb vfb ipk ipk ipk ipk vstr vstr vstr vstr drain drain drain drain drain drain drain drain drain drain drain drain 8dip 8dip 8dip 8dip 8lsop 8lsop 8lsop 8lsop
fsdl0165rn 4 absolute maximum ratings (ta=25 c, unless otherwise specified) note: 1. repetitive rating: pulse width limited by maximum junction temperature 2. l = 51mh, starting tj = 25 c 3. l = 13 h, starting tj = 25 c 4. vsd is shutdown feedback voltage ( see protection section in electrical characteristics ) thermal impedance note: 1. free standing with no heatsink. 2. measured on the gnd pin close to plastic interface. 3. soldered to 0.36 sq. inch(232mm2), 2 oz.(610g/m2) copper clad. characteristic symbol value unit drain current pulsed (1) i dm 4.0 a dc single pulsed avalanche energy (2) e as 95 mj maximum supply voltage v cc,max 20 v analog input voltage range v fb -0.3 to v sd v total power dissipation p d 1.25 w operating junction temperature. t j +150 c operating ambient temperature. t a -25 to +85 c storage temperature range. t stg -55 to +150 c parameter symbol value unit 8dip junction-to-ambient thermal ja (1) 81.50 c/w (3) junction-to-case thermal jc (2) 21.90 c/w
fsdl0165rn 5 electrical characteristics (ta = 25 c unless otherwise specified) parameter symbol condition min. typ. max. unit sense fet section startup voltage (vstr) breakdown bv str v cc =0v, i d =1ma 650 - - v drain-source breakdown voltage bv dss v gs =0v, i d =50 a 650 - - v off-state current (max.rating =660v) i dss v ds =660v, v gs =0v - - 50 a v ds =0.8max.rating v gs =0v, t c =125 c - - 200 a on-state resistance (1) r ds(on) v gs =10v, i d =0.5a - 8.0 10.0 ? input capacitance c iss v gs =0v, v ds =25v, f=1mhz - 250 - pf output capacitance c oss -25- pf reverse transfer capacitance c rss -10- pf turn on delay time t d(on) v ds =325v, i d =1.0a (sense fet switching time is essentially independent of operating temperature) -12- ns rise time t r -4 - ns turn off delay time t d(off) -30- ns fall time t f -10- ns control section output frequency f osc fsdl0165r 45 50 55 khz output frequency modulation f mod 1.0 .1.5 2.0 khz frequency change with temperature (2) --25 c ta 85 c - 5 10 % maximum duty cycle d max fsdl0165r 71 77 83 % minimum duty cycle d min 000% start threshold voltage v start v fb =gnd 11 12 13 v stop threshold voltage v stop v fb =gnd 7 8 9 v feedback source current i fb v fb =gnd 0.7 0.9 1.1 ma internal soft start time t s/s v fb =4v 10 15 20 ms burst mode section burst mode voltages v burh - 0.5 0.6 0.7 v v burl - 0.25 0.35 0.45 v protection section drain to source peak current limit i over max. inductor current 1.06 1.20 1.35 a current limit delay (3) t cld - 500 - ns thermal shutdown t sd - 125 140 - c
fsdl0165rn 6 note: 1. pulse test: pulse width 300us, duty 2% 2. these parameters, although guaranteed, are tested in eds (wafer test) process 3. these parameters, although guaranteed, are not 100% tested in production shutdown feedback voltage v sd 5.5 6.0 6.5 v over voltage protection v ovp 18 19 - v shutdown feedback delay current i delay v fb =4v 3.5 5.0 6.5 a leading edge blanking time t leb 200 - - ns total device section operating current i op v cc =14v 1 3 5 ma start up current i start v cc =0v 0.7 0.85 1.0 ma vstr supply voltage v str v cc =0v 35 - - v
fsdl0165rn 7 comparison between ka5x0165rn and fsdl0165rn function ka5x0265rn fsdl0165rn fsdl0165rn advantages soft-start not applicable 15ms ? gradually increasing current limit during soft-start further reduces peak current and voltage component stresses ? eliminates external components used for soft-start in most applications ? reduces or eliminates output overshoot external current limit not applicable programmable of default current limit ? smaller transformer ? allows power limiting (constant over- load power) ? allows use of larger device for lower losses and higher efficiency. frequency modulation not applicable 1.5khz @50khz ? reduced conducted emi burst mode operation not applicable yes-built into controller ? improve light load efficiency ? reduces no-load consumption ? transformer audible noise reduction drain creepage at package 1,02mm 7.62mm ? greater immunity to arcing as a result of build-up of dust, debris and other contaminants
fsdl0165rn 8 typical performance characteristics (control part) ( these characteristic graphs are normalized at ta = 25 c) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized operating frequency (fosc) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized frequency modulation (f mod ) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized maximum duty cycle (dmax) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized operating supply current (iop) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] nomalized start threshold voltage (vstart) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized stop threshold voltage (vstop)
fsdl0165rn 9 typical performance characteristics (continued) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized feedback source current (ifb) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized peak current limit (iover) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized start up current (istart) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized j-fet start up current (istr) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized burst peak current (iburst) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized over voltage protection (vovp)
fsdl0165rn 10 functional description 1. startup : in previous generations of fairchild power switches (fps tm ) the vstr pin had an external resistor to the dc input voltage line. in this generation the startup resistor is replaced by an internal high voltage current source and a switch that shuts off when 15ms goes by after the supply voltage, vcc, gets above 12v. the source turns back on if vcc drops below 8v. figure 4. high voltage current source 2. feedback control : the fsdl0165rn employs current mode control, shown in figure 5. an opto-coupler (such as the h11a817a) and shunt regulator (such as the ka431) are typically used to implement the feedback network. compar- ing the feedback voltage with the voltage across the rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. when the reference pin voltage of the ka431 exceeds the internal reference voltage of 2.5v, the h11a817a led current increases, thus pulling down the feedback voltage and reducing the duty cycle. this event typically happens when the input voltage is increased or the output load is decreased. 3. leading edge blanking (leb) : at the instant the internal sense fet is turned on, there usually exists a high current spike through the sense fet, caused by the primary side capacitance and secondary side rectifier diode reverse recov- ery. excessive voltage across the rsense resistor would lead to incorrect feedback operation in the current mode pwm control. to counter this effect, the fps tm employs a leading edge blanking (leb) circuit. this circuit inhibits the pwm comparator for a short time (t leb ) after the sense fet is turned on. figure 5. pulse width modulation (pwm) circuit 4. protection circuit : the fps tm has several protective func- tions such as over load protection (olp), over voltage pro- tection (ovp), abnormal over current protection (aocp), under voltage lock out (uvlo) and thermal shutdown (tsd). because these protection circuits are fully integrated inside the ic without external components, the reliability is improved without increasing cost. once the fault condition occurs, switching is terminated and the sense fet remains off. this causes vcc to fall. when vcc reaches the uvlo stop voltage, 8v, the protection is reset and the internal high voltage current source charges the vcc capacitor via the vstr pin. when vcc reaches the uvlo start voltage,12v, the fps tm resumes its normal operation. in this manner, the auto-restart can alternately enable and disable the switching of the power sense fet until the fault condition is elimi- nated. 4.1 over load protection (olp) : overload is defined as the load current exceeding a pre-set level due to an unexpected event. in this situation, the protection circuit should be acti- vated in order to protect the smps. however, even when the smps is in the normal operation, the over load protection circuit can be activated during the load transition. in order to avoid this undesired operation, the over load protection cir- cuit is designed to be activated after a specified time to deter- mine whether it is a transient situation or an overload situation. in conjunction with the ipk current limit pin (if used) the current mode feedback path would limit the current in the sense fet when the maximum pwm duty cycle is attained. if the output consumes more than this maximum power, the output voltage (vo) decreases below the set volt- age. this reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (vfb). if vfb exceeds 3v, the feed- back input diode is blocked and the 5ua i delay current source starts to charge cfb slowly up to vcc. in this condition, vfb continues increasing until it reaches 6v, when the switching operation is ter- minated as shown in figure 6. the delay time for shutdown is the time required to charge cfb from 3v to 6v with 5ua. vin,dc vin,dc vin,dc vin,dc vstr vstr vstr vstr vcc vcc vcc vcc 15ms after uvlo 15ms after uvlo 15ms after uvlo 15ms after uvlo start(>12v) start(>12v) start(>12v) start(>12v) off off off off uvlo <8v uvlo <8v uvlo <8v uvlo <8v on on on on istr istr istr istr j-fet j-fet j-fet j-fet 3 osc vcc vref 2ua 0.9ma v sd r 28r fb gate driver olp d1 d2 vfb* vfb 431 cfb vo
fsdl0165rn 11 figure 6. over load protection 4.2 thermal shutdown (tsd) : the sense fet and the con- trol ic are integrated, making it easier for the control ic to detect the temperature of the sense fet. when the tempera- ture exceeds approximately 140 c, thermal shutdown is acti- vated. 4.3 abnormal over current protection (aocp) : figure 7. aocp function & block even though the fps tm has olp (over load protection) and current mode pwm feedback, these are not enough to protect the fps tm when a secondary side diode short or a transformer pin short occurs. in addition to start-up, soft- start is also activated at each restart attempt during auto- restart and when restarting after latch mode is activated. the fps tm has an internal aocp (abnormal over current pro- tection) circuit as shown in figure 7. when the gate turn-on signal is applied to the power sense fet, the aocp block is enabled and monitors the current through the sensing resis- tor. the voltage across the resistor is then compared with a preset aocp level. if the sensing resistor voltage is greater than the aocp level, pulse by pulse aocp is triggered regardless of uncontrollable leb time. here, pulse by pulse aocp stops sense fet within 350ns after it is activated. 4.4 over voltage protection (ovp) : in case of malfunc- tion in the secondary side feedback circuit, or feedback loop open caused by a defect of solder, the current through the opto-coupler transistor becomes almost zero. then, vfb climbs up in a similar manner to the over load situation, forc- ing the preset maximum current to be supplied to the smps until the over load protection is activated. because excess energy is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. in order to prevent this situation, an over voltage protection (ovp) circuit is employed. in general, vcc is proportional to the output voltage and the fps tm uses vcc instead of directly monitoring the output voltage. if v cc exceeds 19v, ovp circuit is activated resulting in ter- mination of the switching operation. in order to avoid undes- ired activation of ovp during normal operation, vcc should be properly designed to be below 19v. 5. soft start : the fps tm has an internal soft start circuit that increases the feedback voltage together with the sense fet current slowly after it starts up. the typical soft start time is 15msec, as shown in figure 8, where progressive increments of sense fet current are allowed during the start-up phase. the pulse width to the power switching device is progres- sively increased to establish the correct working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output volt- age. it also helps to prevent transformer saturation and reduce the stress on the secondary diode. 1 t 2 t 3 t 4 t t 3v 6v vcc 8v delay current (5ua) charges the cfb delay current (5ua) charges the cfb delay current (5ua) charges the cfb delay current (5ua) charges the cfb fps switching fps switching fps switching fps switching olp following vcc following vcc following vcc following vcc 2 . _ , 8 . 2 , 3 ) 1 ( ); ) 1 ( 1 ( 1 1 fig fb fb fb c c k r v t v r t v in rc t = ? = = ? ? = v t v t t v ua i i t v t t v c t delay delay fb 3 ) 1 ( ) 2 1 ( , 5 ; )) 1 ( ) 2 1 ( ( 2 = ? + = ? + = r sq vsense vf b out dri ver rsense clk drain v aocp pwm comparator aocp comparator leb 1ms 15steps cur rent l i mi t 0.98a 2.15a t drai n current [a]
fsdl0165rn 12 figure 8. soft start function 6. burst operation : in order to minimize power dissipation in standby mode, the fps tm enters burst mode operation. figure 9. circuit for burst operation as the load decreases, the feedback voltage decreases. as shown in figure 10, the device automatically enters burst mode when the feedback voltage drops below v burh (500mv). switching still con- tinues but the current limit is set to a fixed limit internally to mini- mize flux density in the transformer. the fixed current limit is larger than that defined by vfb = v burh and therefore, vfb is driven down further. switching continues until the feedback voltage drops below v burl (300mv). at this point switching stops and the output voltages start to drop at a rate dependent on the standby current load. this causes the feedback volt- age to rise. once it passes v burh (500mv) switching resumes. the feedback voltage then falls and the process repeats. burst mode operation alternately enables and disables switching of the power sense fet thereby reducing switching loss in standby mode. figure 10. circuit for burst operation 7. frequency modulation : emi reduction can be accom- plished by modulating the switching frequency of a switched power supply. frequency modulation can reduce emi by spreading the energy over a wider frequency range than the band width measured by the emi test equipment. the amount of emi reduction is directly related to the depth of the reference frequency. as can be seen in figure 11, the fre- quency changes from 65khz to 69khz in 4ms for the fsdm0265rn. frequency modulation allows the use of a cost effective inductor instead of an ac input mode choke to satisfy the requirements of world wide emi limits. figure 11. frequency modulation waveform drain drain drain drain gnd gnd gnd gnd rsense i_ o ve r sw itch off 5v 3 vcc vcc i delay i fb r 2.5r fb 0.3/0.5v pwm + - 0.5v vcc i b_peak burst normal mosfet mosfet mosfet mosfet current current current current 0.5v switching off current waveform burst operation normal operation feedback 0.3v burst operation switching off 69khz 69khz 67khz 65khz 4khz turn-on turn-off point internal oscillator drain to source voltage vds waveform drain to source current
fsdl0165rn 13 figure 12. ka5-series fps tm full range emi scan(67khz, no frequency modulation) with dvd player set figure 13. fsdx-series fps tm full range emi scan (67khz, with frequency modulation) with dvd player set 8. adjusting current limit function: as shown in fig 14, a combined 2.8k ? internal resistance is connected into the non-inverting lead on the pwm comparator. a external resistance of y on the current limit pin forms a parallel resis- tance with the 2.8k ? when the internal diodes are biased by the main current source of 900ua. figure 14. peak current adjustment for example, fsdx0265rn has a typical sense fet current limit (i over ) of 2.15a. the sense fet current can be limited to 1a by inserting a 2.8k ? between the current limit pin and ground which is derived from the following equations: 2.15: 1 = 2.8k ? : xk ? , x = 1.3k ? , since x represents the resistance of the parallel network, y can be calculated using the following equation: y = x / (1 - (x/2.8k ? )) frequency (mhz) amplitude (db v) cispr2qb cispr2ab frequency (mhz) amplitude (db v) cispr2qb cispr2ab 3 4 pwm comparator sensefet sense ? k 2 ? k 8 . 0 ? a k 900ua 5ua rsense feed back current limit
fsdl0165rn 14 typical application circuit 1. set top box example circuit (13w output power) fsdl0165rn 1 5 ddd svccvfb c7 400v /47u d5 uf4007 r1 47k d6 uf4004 c9 33n 50v i_pk start c8 6.8n/ 1kv r4 30r c6 50v 47uf d15 sb360 d14 d13 egp20d d12 pc817 fod2741a l1 l2 l3 c11 c12 +3.3v +5.0v +17.0v +23.0v 0.4~0.8a 0.2~0.5a 0.01~0.2a 0.005~0.20a c13 c15 c17 c16 c14 1000uf /16v 470uf /10v 1000uf /16v 470uf /10v 470uf /35v 220uf /35v 100uf /50v 100uf /50v r21 r14 r13 r15 330r 800r 6.9k r12 2.7k 1.5k c209 0.1uf/ monolithic lf1 40mh kbp06m 100pf /400v 100pf /400v c2 c1 2a/250v fuse 85vac ~275vac 56k/1/ 4w r3 q1 r19 r20 pc817 tl431az egp20d egp20d 1 3 4 5 8 6 10 11 12 performance summary output power: 13w regulation 3.3v: 5% 5.0v: 5% 17.0v: 7% 23.0: 7% efficiency: 75% no load consumption: 0.12w at 230vac greenfps r5 6kr r15 20r r22 1kr figure15. 13w multiple power supply using fsdl0165rn multiple output, 13w, 85-265vac input power supply: figure 15 shows a multiple output supply typical for high end set-top boxes containing high capacity hard disks for recording. the supply delivers an output power of 13w cont./15w peak (thermally limited) from an input voltage of 85 to 265 vac. efficiency at 9w, 85vac is 75%. the 3.3 v and 5 v outputs are regulated to 5% without the need for secondary linear regulators. dc stacking (the sec- ondary winding reference for the other output voltages is connected to the anode of d15. for more accuracy, connec- tion to the cathode of d15 will be better.) is used to minimize the voltage error for the higher voltage outputs. due to the high ambient operating temperature requirement typical of a set-top box (60 c) the fsdl0165rn is used to reduce con- duction losses without a heatsink. resistor r5 sets the device current limit to limit overload power. leakage inductance clamping is provided by r1 and c8, keeping the drain voltage below 650 v under all condi- tions. resistor r1 and capacitor c8 are selected such that r1 dissipates power to prevent rising of drain voltage caused by leakage inductance. the frequency modulation feature of fsdl0165rn allows the circuit shown to meet cispr2ab with simple emi filtering (c1, lf1 and c2) and the output grounded. the secondaries are rectified and smoothed by d12, d13, d14,and d15. diode d15 for the 3.4v output is a schottky diode to maximize efficiency. diode d14 for the 5 v output is a pn type to center the 5 v output at 5 v. the 3.3 v and 5 v output voltage require two capacitors in parallel to meet the ripple current requirement. switching noise filter- ing is provided by l3, l2 and l1. resistor r15 prevents peak charging of the lightly loaded 23v output. the outputs are regulated by the reference (tl431) voltage in secondary. both the 3.3 v and 5 v outputs are sensed via r13 and r14. resistor r22 provides bias for tl431and r21 sets the over- all dc gain. resistor r21, c209, r14 and r13 provide loop compensation.
fsdl0165rn 15 2. transformer specification 1. transformer specification - schematic diagram (transformer) 2. winding specification no. pin(s f) wire turns winding method n p/2 3 2 0.25 1 22 solenoid winding n 3.3v 6 8 0.3 8 2 stack winding n 5v 10 6 0.3 2 1 stack winding n 16v 11 6 0.3 4 7 solenoid winding n 23v 12 11 0.3 2 3 solenoid winding n p/2 2 1 0.25 1 22 solenoid winding n b 4 5 0.25 1 10 center winding 3. electric characteristic closure pin spec. remarks inductance 1 - 3 800uh 10% 1khz, 1v leakage l 1 - 3 15uh max. 2nd all short 4. bobbin & core. core: eer2828 bobbin: eer2828 n p/2 n 3.3v n p/2 n b 3mm 6mm bottom top n 5v n 23v n 17v 1 2 3 4 5 6 7 8 10 11 12
fsdl0165rn 16 layout considerations figure 15. layout considerations for fsdl0165rn using 8dip #1 : gnd #2 : vcc #3 : vfb #4 : ipk #5 : vstr #6 : drain #7 : drain #8 : drain surface mounted copper area for heat sinking y1- capacitor + - dc out dc_link capacitor
fsdl0165rn 17 package dimensions 8dip
fsdl0165rn 18 package dimensions (continued) 8lsop
fsdl0165rn 19 ordering information product number package marking code bv dss f osc r ds(on) fsdl0165rn 8dip dl0165r 650v 50khz 8.0 ? fsdl0165rl 8lsop dl0165r 650v 50khz 8.0 ?
fsdl0165rn 6/17/04 0.0m 001 ? 2004 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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